Semiconductor based non-volatile memories are useful both in terms of data storage and as an alternative to rotating disk memories. Memories based on flash EEPROM cells have found increasing applications in computers as well as consumer devices such as cameras, mp3 players, and PDAs. The cost of flash EEPROM memories has decreased to the point that such memories are being used as a replacement for disk drives in computers. Semiconductor disk drives are particularly attractive for laptop computers because they require significantly lower power, are shock resistant, and are typically faster than the conventional disk drives that are utilized in such systems.
However, these memories have a number of drawbacks. First, the cost of these memories is still an order of magnitude greater than the cost of a conventional disk drive having the same capacity. In one class of memory, one bit is stored in each memory cell. The memory cell includes an EEPROM cell and a gate that connects the EEPROM to a bit line that receives a signal indicative of the amount of charge stored on the gate of the transistor in the EEPROM. The cells are read out in a non-destructive manner; however, the time needed to read the contents of a cell is much greater than that needed to read a conventional semiconductor memory. To overcome the slow read times, a large number of cells are read in parallel. In essence, a unit of memory, analogous to a track on a conventional rotating memory, is read at once. The memory cells associated with each “track” are located on the same row of cells in the memory, which is organized as a plurality of rows and columns. Since the time to address a row is much smaller than the average time needed to position a sector under the read head of a rotating memory, these semiconductor memories have an extremely small seek time. Unfortunately, the time needed to write a memory cell limits the rate at which data can be written to the memory to times that are significantly longer than the write times for conventional high-speed disk drives.
Second, the number of write cycles that can be executed on each cell before the memory fails is significantly less than that of conventional disk drives. To overcome this problem complex storage algorithms are used to ensure that the writes are not concentrated in any particular group of cells.
Third, the cost of providing a semiconductor disk drive that has write times that are as good or better than the fastest conventional disk drives further increases the cost of the drives to the point where one drive can cost more than a conventional personal computer system. In the case of laptop computers, power considerations dictate that the conventional drives used in laptops are significantly slower than the high speed drives used in workstations. Hence, the increase in speed and reduced power considerations make semiconductor drives attractive for laptops.
Finally, flash memory is confined to silicon fabrication regimes that are not easily adapted to environments in which high energy x-rays or other high-energy radiation is present. Hence, these memories are not useful in such high radiation environments.
Ferroelectric memories are an alternative to flash-based memories and have the potential to address many of the problems described above. In one class of conventional ferroelectric memory the data is stored in the remanent polarization of one or more capacitors in each memory cell. The time to write a memory cell is much faster than the time to write a flash cell, and hence, the problems associated with slow write times in flash cells are avoided. In addition, the memory cells can be subjected to many more write cycles than flash based memory cells and can be constructed in fabrication systems that are radiation resistant since it takes many more hits to depolarize a capacitor than it takes to alter the charge on the floating gate of a flash memory cell.
The simplest ferroelectric memory has one ferroelectric capacitor and a gate transistor for connecting that capacitor to a bit line. The memory is read by applying a voltage across the capacitor and sensing the amount of charge that is released onto the bit line. If the memory bit is in one state, the polarization flips and a charge is released onto the bit line. In the other state, the polarization remains the same, and a much smaller charge appears on the bit lines. In a large memory, the cells are organized in a rectangular array of rows and columns. All of the cells in a column are connected to a bit line that terminates in circuitry that detects the charge released when a cell in that column is interrogated. This design places the sense amplifiers at a significant distance from the ferroelectric capacitors and requires that the ferroelectric capacitor drive a significant capacitance that is inherent in the bit lines. Since the amount of charge that is released is large when the dielectric in the ferroelectric capacitor state flips, the bit line circuitry presents challenges. Furthermore, the readout operation destroys the data if the cell is in the state in which the polarization flips; hence, the contents of the memory cell must be re-written each time the cell is read, which further complicates the bit line circuitry.
Many of the problems associated with these simple memory cells can be avoided by using memory designs in which active circuitry is provided in each memory cell. The local circuitry provides active gain and charge-to-voltage conversion that mitigates the problems associated with reading a small charge signal at a distance over a bit line. In addition, the rewriting of the ferroelectric capacitors in the memory cell is provided by the local circuitry, and hence, the timing issues presented by the simple one capacitor, one transistor memory cell are significantly reduced. One class of active memory cell is configured as a latch. Unfortunately, the silicon area needed to implement a conventional ferroelectric latch memory cell is much greater than that needed to implement the one capacitor, one transistor cell described above. For example, a conventional latch-based ferroelectric memory cell requires at least two ferroelectric capacitors and six transistors.